Cell broadband engine (CellBE for short hereinafter) processor is a kind of microprocessor utilizing parallel processing. Generally, basic configuration of a CellBE processor comprises a Power Processing Element (PPE), eight Synergistic Processing Elements (SPEs), a Memory Flow Control (MFC), an Internal Interrupt Control (IIC), and a Main Memory. Computing components of the CellBE processor are PPE and SPEs. Componential parts of the CellBE processor are connected via high-speed bus of “Elements Interconnection Bus” (EIB). Any two of the eight SPEs may exchange data through a high-speed bus of 25.6 GB therebetween, while only a bus of 25.6 GB totally is between SPEs and the main memory. Bus transfers between SPEs and bus transfers between respective SPEs and the main memory may be in parallel. CellBE processor is applicable to various applications from handhold devices to main computers.
CellBE processor presents a step change in computer architecture by eight SPEs which may process in parallel, thereby improving computer performance of computer greatly. In order to solve memory wall problem in CellBE processor, each of SPEs in the CellBE processor is provided with a specific local storage and may only access its local storage (LS) directly. Introduction of LS can reduce the memory latency. Usually, however, size of LS is 256 KB, and such size of storage space brings trouble for developers for its limitation for programs' binary size. Besides, such SPEs lack cache, which will decrease computing performance of CellBE processor for processing data massive application, such as high performance computing, digital media, and financial applications.
To solve the above problems, existing CellBE processor incorporates a specific physical cache for SPE. Although the computing performance is improved, architecture of the CellBE processor is more complex, resulting in increase of cost. Another approach is soft-cache. This approach uses part of LS as a soft-cache. Drawback for this solution is in that the technology decreases available space of LS, and once size of a program is becoming large, the soft-cache will not be usable.
Further, another problem in the related art is persistent data management. Due to the limited size of LS, most persistent data must be put into main memory managed by PPE. There are several shortcomings for communication with the main memory. Firstly, the processing in PPE is probably switched out by OS, and communication overhead between PPE and SPE will increase. Secondly, data in the main memory may be swapped out into hard disk swap partition, and latency will be increased. Thirdly, irregular data movement is easily to cause a cache inconsistent problem, such as cache false sharing.
To solve at least one of above problems, the present invention provides an effective persistent data management method to enhance the performance and utilization of software management cache.